Junior ASIC Physical Design Engineer / 19861BR

Deadline: 10 April 2019

Employment term: Permanent

Category: Hardware Design / Engineering

Job type: Full time

Location: Yerevan

Job description:

The Mixed-Signal IP Design organization is seeking a highly motivated individual for a full time internship. Responsibilities include floorplanning , physical synthesis, clock tree generation, routing, extraction, timing closure, DFT, signal integrity avoidance, analysis and repair, and manufacturing verification. The individual will contribute on the implementation and technology retargeting for a variety of mixed signal IP products and test-chips at 32nm, 28 and below. This requires close interaction and collaborative team work with multiple functional groups (front end, analog, application). 

The successful candidate:
- has engineering understanding of the underlying concepts of IC design
- has knowledge of the full design cycle from RTL to GDSII
- is eager to become an expert with the physical implementation flows and methodologies in deep sub-micron designs 
- has academic and practical exposure in high performance digital design and CAD, high-speed design, low-power design, high speed clock design and distribution, timing closure, signal integrity.
- has good software and scripting skills; knowledge of CAD automation methods.  
- The candidate must have English speaking level allowing interaction with the larger product team to understand design constraints, deliverable formats, and customer requirements
- The candidate must be able to follow defined design methodologies and processes to implement and deliver on schedule.
This position is open for Engineers between 0 and 2 years of experience.

Professional skills

CAD

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Contact details

Website։ https://www.synopsys.com/company/contact-synopsys/office-locations/armenia.html

Phone: (010) 492-100

Address: , Armenia

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