Instigate Semiconductor

Job description:

You will become part of a strong development team in the field of FPGA chip design.

You will design and integrate custom IPs such as: GPIO, I3C, Quad SPI, JTAG, RISC-V CPU, AMBA bus interconnect and NoC. Work on fixing bugs in already existing IP blocks, as well as writing detailed design specifications for newly created blocks.

You will work to create SDC timing constraints, perform block-level STAs and LECs, and support the activities of PNR engineers.

You will work with experienced teams locally and with people from different locations around the world.

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Job responsibilities

• ASIC Core Blocks Design
• Creating RTL to integrate various components (e.g. RiscV CPU, AMBA switch/NOC infrastructure, USB Core,... )
• writing detailed design implementation and specification
• Knowledge on ASIC Implementation flows including Synthesis and Timing analysis
• Timing constraint creation
• Support off logic verification activities
• Support off PNR process
• Block level STA and LEC sign off
• AXI to proprietary internal bus structure
• Clock monitoring blocks and other logic design
• DDR controller integration
• Bring a self-motivated and enthusiastic approach that will achieve any new requirements and overcome all challenges
• Ability to work independently and to schedule requirements.

Required qualifications

• BS/MS degree in ECE/EE from a reputed university.
• 5+ (8+ for Lead) years of relevant experience.
• Strong knowledge on digital fundamentals and understanding of FPGA/ASIC custom chip flow.
• Hands on knowledge on Verilog/SystemVerilog
• Familiarity with RiscV or ARM CPUs and AMBA Bus Interconnect.
• Familiarity with different interfaces such as Ethernet, USB, SD/MMC, PCIe, DDR/LPDDR
• Familiarity with security related functions, encryption, decryption etc.
• Experience with UNIX shell scripting, tcl and python scripting
• Experience on writing a detailed design implementation specification
• Good analytical, oral, and written communication skills
• Work with teams to optimize verification quality
• Review the Code with peers;
• Detail-oriented, self-motivated individual with strong analytical and research skills
• Be a mentor for automation teammates
• Positive attitude, enthusiasm, motivation, and desire for continuous improvement

Required candidate level: Senior

Additional information