Junior FPGA Logical Verification engineer

Deadline: 12 May 2021

Employment term: Permanent

Category: Software development

Job type: Full time

Location: Yerevan

Job description:

  • Be responsible for developing test-benches , test cases and verification flow components for Soc based FPGA
  • Write verification specifications, verification plans, and documentation
  • Develop test bench and automate regression plans
  • Develop tests with software/firmware flow used in SoC FPGA verification
  • Develop Behavioral models using Verilog and VHDL
  • Develop Coverage driven Verification flows
  • Contribute on test development for SoC FPGA fullchip level verification

Required qualifications

  • Familiarity on RTL Verification

  • Familiarity on digital fundamentals and understanding of FPGA/ custom chip flow

  • Knowledge on Verilog and VHDL

  • Experience with UNIX shell scripting and Python scripting

  • Familiarity with FPGA programming and related software usage with Firmware handling knowledge is a plus

  • Good analytical and problem solving skills

  • Good written and verbal communication in English.

Required candidate level: Junior

Additional information

Interested candidates should send their CV to [email protected] email address indicating the position title in the subject line of the email.

Competitive salary depending on experience and skills.

Please clearly mention that you have heard of this job opportunity on staff.am

Professional skills

Unix

Verilog

C++

QT

Soft skills

Positive attitude

Teamwork

Self-motivation

Hardworking

Share this job via your favorite social media channel.