Synopsys Armenia

Описание работы

We are looking for ASIC Physical Design Lead and Manager. If you’re ready to excel, innovate, and fit a leadership role in physical design for IP, Subsystem or SoC, we’d like to welcome you to our Digital Implementation team in Yerevan, Armenia.

/ru/rd-manager-40182br-6

Обязанности

• You will be a crucial part of a truly global organization that has personality, enthusiasm, and fun culture with diversity. You will have all you need to develop technical leadership and grow a strong team. There is an enormous opportunity for professional and personal growth in our innovative organization. If you get excited about building new things and working across discipline lines, then look no more for your next career step.
• Manage a team of Physical Design Engineers developing a variety of high-performance interface IPs, test chips and subsystem (e.g. Serdes/DDR/HDMI/MIPI/USB etc.) in advanced process nodes (e.g. 7nm/5nm/3nm etc.).
• Drive all aspects of project execution from RTL to GDS including Synthesis, Floor Planning, Power Analysis and Planning, CTS, Placement and Routing, STA, EMIR Signoff and Physical Verification meeting schedule and design goals.
• Lead in the interactions and collaborations with cross-functional teams to understand the project scope and requirements, identify challenges and risks, and develop feasible plans including allocating proper resources, driving feasibility study, tracking schedule and progress to ensure timely deliveries with the best quality.
• Develop and improve physical design methodologies, flows, practice guidelines and automation for various implementation steps by leveraging Synopsys EDA ecosystem.
• Motivate and grow the team, hire new talents, and design training plan.

Требования

• A Master’s degree or equivalent or higher in Electrical Engineering, Computer Science, or related field.
• 7 years of hands-on experience in ASIC physical implementation and industry-standard EDA tools with recent contribution to project tape-outs, as a technical lead or/and a design manager.
• Solid engineering understanding of the underlying concepts of IC design, implementation flows and sign-off methodologies for deep submicron design.
• Proven track record of managing physical design team for on-time delivery.
• Strong knowledge of industry standard data file formats including Verilog, GDS, LEF, DEF, SDF, LIB, UPF, CPM, CMM.
• Familiarity with scripting and programming including TCL, Make, Unix Shell, Perl, Python.
• Good written and verbal communication in English.
• In-depth understanding of logical bottlenecks impacting timing closure and methods to overcome these challenges.
• Proficiency in one or more of the following: TCL, Make, Unix Shell, Perl, Python scripting.
• Experience with Synopsys tools including Design Compiler, IC Compiler (2), Fusion Compiler, Prime Time, ICV.
• Excellent communication skills with the ability to think and organize communication at different levels of abstraction.

Требуемый уровень кандидата: Уровень С

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