Junior AMS Layout Design Engineer / 21724BR

Deadline: 25 August 2019

Employment term: Permanent

Category: Hardware Design / Engineering

Job type: Full time

Location: Yerevan

Job description:

Layout design and DRC/LVS verification of NVM memory blocks. These include MTP/OTP memories as well as IP/Chip development and verification.  Close work with analog design engineers.

1. Analog  layout design and verification background . 
2. Demonstrates good analysis and problem-solving skills.
3. Knowledge  of layout development /verification tools is a  plus . 
4. Good English written and verbal communication skills.

Professional skills



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Contact details

Website https://www.synopsys.com/company/contact-synopsys/office-locations/armenia.html

Phone: (010) 492-100


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